Just out of curiousity, do you know what's the delay between chip-select cycles while exercising the SPI port Linux.
Example:
1) start timer
2) Chip Select down
3) Send/Receive 1 byte
4) Chip Select Up
5) stop timer
Just out of curiousity, do you know what's the delay between chip-select cycles while exercising the SPI port Linux.
Example:
1) start timer
2) Chip Select down
3) Send/Receive 1 byte
4) Chip Select Up
5) stop timer