I understand there is a nice flat mode in IA32e mode that can address 64 bits for offset and base of seg reg, but that's I (?) guess only for LDTR GDTR IDTR or is it for all the seg regs too? I thought all the seg regs were 16-bit?
what does the limit register do, what is it, how many bits is it, how does it fit into the addressing scheme exactly, how is it loaded (through special instructions?), and where do I find documentation on it that describes what it's for and how it works? I tried looking through the docs, but did not find, maybe I just got lost.
at least with this info, if it's the compiler's fault, I can help the folks fix the compiler.
I am running into compiler segmentation faults because my functions are too big (with a 64-bit target, 64-bit host compiler??? you have got to be kidding) I am guessing it's the old 64k limitations we used to have with 8088. are we still having the same issues with today's 64-bit procs? what happens when we go to 128-bit or 256-bit? I already need 128-bit ints (128-bit native registers) in a standard desktop processor in order to process SI and IEC units without mangling them.
I am making a formal request to fix the small limitations of the 64-bit proc. my function was only 1000 lines of C++, but was full of if's and strings on every line (it was a formatted output generator based on format strings). I think I can reduce my code here, but there is another program I have where I cannot reduce my code, and it has a huge main() with the same problem, and it cannot be modularized to my knowledge and I can't continue to write my embedded database application with things the way they are now.
please fix with new CPU designs or microcode changes. thanks. I wouldn't even mind if 128 bits were loaded from memory 64 bits at a time just as long as I had the functionality.